Worst-case circuit analysis

Worst-case circuit analysis (WCCA or WCA) is a cost-effective means of screening a design to ensure with a high degree of confidence that potential defects and deficiencies are identified and eliminated prior to and during test, production, and delivery.

It is a quantitative assessment of the equipment performance, accounting for manufacturing, environmental and aging effects. In addition to a circuit analysis, a WCCA often includes stress and derating analysis, failure modes and effects criticality (FMECA) and reliability prediction (MTBF).

The specific objective is to verify that the design is robust enough to provide operation which meets the system performance specification over design life under worst-case conditions and tolerances (initial, aging, radiation, temperature, etc.).

Stress and de rating analysis is intended to increase reliability by providing sufficient margin compared to the allowable stress limits. This reduces overstress conditions that may induce failure, and reduces the rate of stress-induced parameter change over life. It determines the maximum applied stress to each component in the system.

General information

A worst-case circuit analysis should be performed on all circuitry that is safety and financially critical. Worst-case circuit analysis is an analysis technique which, by accounting for component variability, determines the circuit performance under a worst-case scenario (under extreme environmental or operating conditions). Environmental conditions are defined as external stresses applied to each circuit component. It includes temperature, humidity or radiation. Operating conditions include external electrical inputs, component quality level, interaction between parts, and drift due to component aging.

WCCA helps in the process of design reliability into hardware for long-term field operation. Electronic piece-parts fail in two distinct modes:

Out-of-tolerance limits: Through this, the circuit continues to operate, though with degraded performance, and ultimately exceeds the circuit's required operating limits.

Catastrophic failures may be minimized through MTBF, stress and derating, and FMECA analyses that help to ensure that all components are properly derated, as well as that degradation is occurring “gracefully...”

A WCCA permits you to predict and judge the circuit performance limits beneath all of the combos of half tolerances.

There are many reasons to perform WCCA. Here are a few that may be impactful to schedule and cost.

Design Verification and ReliabilityVerifies circuit operation and quantifies the operating margins over part tolerances and operating conditions - Will the circuit perform its functions and meet specifications?/WCCA quantifies the risk
Improve circuit performance - Determines the sensitivity of components to certain characteristics or tolerances in order to better optimize/understand a design and what drives performance
Verifies that a circuit interfaces with another design properly
Determines the impact of part failures or out of tolerance modes
Test Cost ReductionEvaluate performance aspects that are difficult, expensive or impossible to measure (i.e. determines the impact of input stimulus and output loading so as not to damage hardware)
Helps set ATP limits
Verifies Select-in-Test adjustments and if they are needed/what their limits should be
Reduces the amount and scope of testing
Parts AssessmentDetermines if parts are suitable for their intended use (are they too cheap, too expensive, right characteristics) or if a new technology can be used
Supports/sets critical parameters and SCD requirements/screening definitions
Models can be used to perform Single Event Transient (SET) analyses
Schedule, Cost, or Contractual Risk ReductionReduces board spins - determines the impact of late stage design or part changes
Verifies the impact of changes to heritage circuits or part replacements
Allows you to obtain better insurance rates or reduce contractual liabilities
Analysis helps you avoid catastrophic or costly incidents


Worst-case analysis is the analysis of a device (or system) that assures that the device meets its performance specifications. These are typically accounting for tolerances that are due to initial component tolerance, temperature tolerance, age tolerance and environmental exposures (such as radiation for a space device). The beginning of life analysis comprises the initial tolerance and provides the data sheet limits for the manufacturing test cycle. The end of life analysis provides the additional degradation resulting from the aging and temperature effects on the elements within the device or system.

This analysis is usually performed using SPICE, but mathematical models of individual circuits within the device (or system) are needed to determine the sensitivities or the worst-case performance.[1] A computer program is frequently used to total and summarize the results.

A WCCA follows these steps:

  1. Generate/obtain circuit model
  2. Obtain correlation to validate model
  3. Determine sensitivity to each component parameter
  4. Determine component tolerances
  5. Calculate the variance of each component parameter as sensitivity times absolute tolerance
  6. Use at least two methods of analysis (e.g. hand analysis and SPICE or Saber, SPICE and measured data) to assure the result
  7. Generate a formal report to convey the information produced

The design is broken down into the appropriate functional sections. A mathematical model of the circuit is developed and the effects of various part/system tolerances are applied. The circuit's EVA and RSS results are determined for beginning-of-life and end-of-life states.

These results are used to calculate part stresses and are applied to other analysis. In order for the WCCA to be useful throughout the product’s life cycle, it is extremely important that the analysis be documented in a clear and concise format. This will allow for future updates and review by other than the original designer. A compliance matrix is generated that clearly identifies the results and all issues.

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