Register allocation

In compiler optimization, register allocation is the process of assigning a large number of target program variables onto a small number of CPU registers.

Register allocation can happen over a basic block (local register allocation), over a whole function/procedure (global register allocation), or across function boundaries traversed via call-graph (interprocedural register allocation). When done per function/procedure the calling convention may require insertion of save/restore around each call-site.



Different number of registers in the most common architectures
Architecture 32 bits 64 bits
ARM 15 31
Intel x86 8 16
MIPS 32 32
RISC-V 16/32 32

In many programming languages, the programmer may use any number of variables. The computer can quickly read and write registers in the CPU, so the computer program runs faster when more variables can be in the CPU's registers.[1] Also, sometimes code accessing registers is more compact, so the code is smaller, and can be fetched faster if it uses registers rather than memory. However, the number of registers is limited. Therefore, when the compiler is translating code to machine-language, it must decide how to allocate variables to the limited number of registers in the CPU.[2][3]

Not all variables are in use (or "live") at the same time, so, over the lifetime of a program, a given register may be used to hold different variables. However, two variables in use at the same time cannot be assigned to the same register without corrupting one of the variables. If there are not enough registers to hold all the variables, some variables may be moved to and from RAM. This process is called "spilling" the registers.[4] Over the lifetime of a program, a variable can be both spilled and stored in registers: this variable is then considered as "split".[5] Accessing RAM is significantly slower than accessing registers [6] and so a compiled program runs slower. Therefore, an optimizing compiler aims to assign as many variables to registers as possible. A high "Register pressure" is a technical term that means that more spills and reloads are needed; it is defined by Braun et al. as "the number of simultaneously live variables at an instruction".[7]

In addition, some computer designs cache frequently-accessed registers. So, programs can be further optimized by assigning the same register to a source and destination of a move instruction whenever possible. This is especially important if the compiler is using an intermediate representation such as static single-assignment form (SSA). In particular, when SSA is not fully optimized it can artificially generate additional move instructions.

Components of register allocation

Register allocation consists therefore in choosing where to store the variables at runtime, i.e. inside or outside registers. If the variable is to be stored in registers, then the allocator needs to determine in which register(s) this variable will be stored. Eventually, another challenge is to determine the duration for which a variable should stay at the same location.

A register allocator, disregarding the chosen allocation strategy, can rely on a set of core actions to address these challenges. These actions can be gathered in three different categories:[8]

Move insertion
This action consists in increasing the number of move instructions between registers, i.e. make a variable live in different registers during its lifetime, instead of one. This occurs in the split live range approach.
This action consists of storing a variable into memory instead of registers.[9]
This action consists of assigning a register to a variable.[10]
This action consists of limiting the number of moves between registers, thus limiting the total number of instructions. For instance, by identifying a variable live across different methods, and storing it into one register during its whole lifetime.[9]

Mostly, a lot of register allocation approaches try to specifically optimize one or the other category of actions.

Common problems raised in register allocation

Register allocation raises several problems that can be tackled (or avoided) by different register allocation approaches. Three of the most common problems are identified as follows:

In some architectures, assigning a value to one register can affect the value of another: this is called aliasing. For example the x86 architecture has four general purpose 32-bit registers that can also be used as 16-bit or 8-bits registers.[11] In this case, assigning a 32-bits value to the eax register will affect the value of the al register.
This problem is an act to force some variables to be assigned to particular registers. For example, in PowerPC architecture parameters are commonly passed in R3-R10 and the return value is passed in R3.[12]
Chaitin et al. showed that register allocation is a NP-complete problem. Indeed, they reduced the problem as a graph-coloring problem, where each node represents a variable and color represents the number of machine registers. That graph can be arbitrary, thereby proving the NP-completeness of the problem.[13]

Register allocation techniques

Register allocation can happen over a basic block of code: it is said to be "local", and was first mentioned by Horwitz et al.[14] As basic blocks do not contain branches, the allocation process is thought to be fast, because the management of control flow graph merge points in register allocation reveals itself a time-consuming operation.[15] However, this approach is thought not to produce as optimized code as the "global" approach, which operates over the whole compilation unit (a method or procedure for instance).[16]

Graph-coloring allocation

Graph-coloring allocation is the predominant approach to solve register allocation.[17][18] It was first proposed by Chaitin et al.[19] In this approach, nodes in the graph represent live ranges (variables, temporaries, virtual/symbolic registers) that are candidates for register allocation. Edges connect live ranges that interfere , i.e., live ranges that are simultaneously live at at least one program point. Register allocation then reduces to the graph coloring problem in which colors (registers) are assigned to the nodes such that two nodes connected by an edge do not receive the same color.[20]

Using liveness analysis, an interference graph can be built. The interference graph which is an undirected graph where the nodes are the program's variables is used to model which variables cannot be allocated to the same register.[21]


The main phases in a Chaitin-style graph-coloring register allocator are:[18]

  1. Renumber: discover live range information in the source program.
  2. Build: build the interference graph.
  3. Coalesce: merge the live ranges of non-interfering variables related by copy instructions.
  4. Spill cost: compute the spill cost of each variable. This assesses the impact of mapping a variable to memory on the speed of the final program.
  5. Simplify: construct an ordering of the nodes in the inferences graph
  6. Spill Code: insert spill instructions, i.e loads and stores to commute values between registers and memory.
  7. Select: assign a register to each variable.

Drawbacks and further improvements

The graph-coloring allocation has three major drawbacks. First, it relies on graph-coloring, which is an NP-complete problem, to decide which variables are spilled. Finding a minimal coloring graph is indeed an NP-complete problem.[22] Second, unless live-range splitting is used, evicted variables are spilled everywhere: store (respectively load) instructions are inserted as early (respectively late) as possible, i.e., just after (respectively before) variable definitions (respectively uses). Third, a variable that is not spilled is kept in the same register throughout its whole lifetime.[23]

On the other hand, a single register name may appear in multiple register classes, where a class is a set of register names that are interchangeable in a particular role. Then, multiple register names may be aliases for a single hardware register[24] Finally, graph coloring is an aggressive technique for allocating registers, but is computationally expensive due to its use of the interference graph, which can have a worst-case size that is quadratic in the number of live ranges.[25] The traditional formulation of graph-coloring register allocation implicitly assumes a single bank of non-overlapping general-purpose registers and does not handle irregular architectural features like overlapping registers pairs, special purpose registers and multiple register banks.[26]

One later improvement of Chaitin-style graph-coloring approach was found by Briggs et al.: it is called conservative coalescing. This improvement adds a criterion to decide when two live ranges can be merged. Mainly, in addition to the non-interfering requirements, two variables can only be coalesced if their merging will not cause further spilling. Briggs et al. introduces a second improvement to Chaitin's works which is biased coloring. Biased coloring tries to assign the same color in the graph-coloring to live range that are copy related.[18]

Linear Scan

Linear scan is another global register allocation approach. It was first proposed by Poletto et. al in 1999.[27] In this approach, the code is not turned into a graph. Instead, all the variables are linearly scanned to determine their live range, represented as an interval. Once the live ranges of all variables have been figured out, the intervals are traversed chronologically. Although this traversal could help identifying variables whose live ranges interfere, no interference graph is being built and the variables are allocated in a greedy way.[25]

The motivation for this approach is speed; not in terms of execution time of the generated code, but in terms of time spent in code generation. Typically, the standard graph coloring approaches produce quality code, but have a significant overhead,[28][29] the used graph coloring algorithm having a quadratic cost.[30] Owing to this feature, linear scan is the approach currently used in several JIT compilers, like the Hotspot compiler, V8 and Jikes RVM.[5]

Pseudo code

This describes the algorithm as first proposed by Poletto et al.[31]

         active ← {}
         foreach live interval i, in order of increasing start point
           if length(active)=R then
                   register[i] ← a register removed from pool of free registers
                   add i to active, sorted by increasing end point
         foreach interval j in active, in order of increasing end point
           if endpoint[j] ≥ startpoint[i] then
           remove j from active
           add register[j] to pool of free registers
         spill ← last interval in active
         if endpoint[spill] > endpoint[i] then
                   register[i] ← register[spill]
                   location[spill] ← new stack location
                   remove spill from active
                   add i to active, sorted by increasing end point
                   location[i] ← new stack location

Drawbacks and further improvements

However, the linear scan presents two major drawbacks. First, due to its greedy aspect, it does not take lifetime holes into account, i.e. "ranges where the value of the variable is not needed".[32][33] Besides, a spilled variable will stay spilled for its entire lifetime.

Lots of other research works followed up on the Poletto's linear scan algorithm. Traub et al., for instance, proposed an algorithm called second-chance binpacking aiming at generating code of better quality.[34][35] In this approach, spilled variables get the opportunity to be stored later in a register by using a different heuristic from the one used in the standard linear scan algorithm. Instead of using live intervals, the algorithm relies on live ranges, meaning that if a range needs to be spilled, it is not necessary to spill all the other ranges corresponding to this variable.

Linear scan allocation was also adapted to take advantage from the SSA form: the properties of this intermediate representation are used to make the allocation algorithm simpler.[36] First, the time spent in data flow graph analysis, aimed at building the lifetime intervals, is reduced, namely because variables are unique.[37] It consequently produces shorter live intervals, because each new assignment corresponds to a new live interval.[38][39]


The problem of optimal register allocation is NP-complete. As a consequence, compilers employ heuristic techniques to approximate its solution.

Chaitin et al. discuss several ideas for improving the quality of spill code. They point out that certain values can be recomputed in a single instruction and that required operand will always be available for the computation. They call these exceptional values "never-killed" and note that such values should be recalculated instead of being spilled and reloaded. They further note that an uncoalesced copy of a never-killed value can be eliminated by recomputing it directly into the desired register.[40]

These techniques are termed rematerialization. In practice, opportunities for rematerialization include:

  • immediate loads of integer constants and, on some machines, floating-point constants,
  • computing a constant offset from the frame pointer or the static data area, and
  • loading non-local frame pointers from a display.[40]

Briggs and Al extends Chaitin's work to take advantage of rematerialization opportunities for complex, multi-valued live ranges. They found that each value needs to be tagged with enough information to allow the allocator to handle it correctly. Briggs's approach is the following: first, split each live range into its component values, then propagate rematerialization tags to each value, and form new live ranges from connected values having identical tags.[40]


In the context of register allocation, coalescing is the act of merging variable-to-variable move operations by allocating those two variables to the same location. The coalescing operation takes place after the interference graph is built. Once two nodes have been coalesced, they must get the same color and be allocated to the same register, once the copy operation becomes unnecessary.[41]

Doing coalescing might have both positive and negative impacts on the colorability of the interference graph.[9] For example, one negative impact that coalescing could have on graph inference colorability is when two nodes are coalesced, as the result node will have a union of the edges of those being coalesced.[9] A positive impact of coalescing on inference graph colorability is, for example, when a node interferes with both nodes being coalesced, the degree of the node is reduced by one which leads to improving the overall colorability of the interference graph.[42]

There are several coalescing heuristics available:[43]

Aggressive coalescing
it was first introduced by Chaitin original register allocator. This heuristic aims at coalescing any non-interfering, copy-related nodes.[44] From the perspective of copy elimination, this heuristic has the best results.[45] On the other hand, aggressive coalescing could impacts the inference graph colorability.[42]
Conservative Coalescing
it mainly uses the same heuristic as aggressive coalescing but it merges moves if, and only if, it does not compromise the colorability of the interference graph.[46]
Iterated coalescing
it removes one particular move at the time, while keeping the colorability of the graph.[47]
Optimistic coalescing
it is based on aggressive coalescing, but if the inference graph colorability is compromised, then it gives up as few moves as possible.[48]

Mixed approaches

Hybrid allocation

Some other register allocation approaches do not limit to one technique to optimize register's use. Cavazos, for instance, proposed a solution where it is possible to use both the linear scan and the graph coloring algorithms.[49] In this approach, the choice between one or the other solution is determined dynamically: first, a machine learning algorithm is used "offline", that is to say not at runtime, to build an heuristic function that determine which allocation algorithm need to be used. The heuristic function is then used at runtime; in light of the code behavior, the allocator can then chose between one of the two available algorithms.[50]

Trace register allocation is a recent approach developed by Eisl et al.[3][5] This technique handles the allocation locally: it relies on dynamic profiling data to determine which branches will be the most frequently used in a given control flow graph. It then infers a set of "traces" (i.e. code segments) in which the merge point is ignored in favor of the most used branch. Each trace is then independently processed by the allocator. This approach can be considered as hybrid because it is possible to use different register allocation algorithms between the different traces.[51]

Split allocation

Split allocation is another register allocation technique that combines different approaches, usually considered as opposite. For instance, the hybrid allocation technique can be considered as split because the first heuristic building stage is performed offline, and the heuristic use is performed online.[25] In the same fashion, B. Diouf et al. proposed an allocation technique relying both on offline and online behaviors, namely static and dynamic compilation.[52][53] During the offline stage, an optimal spill set is first gathered using Integer Linear Programming. Then, live ranges are annotated using the compressAnnotation algorithm which relies on the previously identified optimal spill set. Register allocation is performed afterwards during the online stage, based on the data collected in the offline phase.[54]

In 2007, Bouchez et al suggested as well to split the register allocation in different stages, having one stage dedicated to spilling, and one dedicated to coloring and coalescing.[55]

Comparison between the different techniques

Several metrics have been used to assess the performance of one register allocation technique against the other. Register allocation has typically to deal with a trade-off between code quality, i.e. code that executes quickly, and analysis overhead, i.e. the time spent determining analyzing the source code to generate code with optimized register allocation. From this perspective, execution time of the generated code and time spent in liveness analysis are relevant metrics to compare the different techniques.[56]

Once relevant metrics have been chosen, the code on which the metrics will be applied should be available and relevant to the problem, either by reflecting the behavior of real-world application, or by being relevant to the particular problem the algorithm wants to address. The more recent articles about register allocation uses especially the Dacapo benchmark suite.[57]

See also


  1. Ditzel & McLellan 1982, p. 48.
  2. Runeson & Nyström 2003, p. 242.
  3. Eisl et al. 2016, p. 14:1.
  4. Chaitin et al., p. 47.
  5. Eisl et al. 2016, p. 1.
  6. "Latency Comparison Numbers in computer/network". Retrieved 8 January 2019.
  7. Braun & Hack 2009, p. 174.
  8. Koes & Goldstein 2009, p. 21.
  9. Bouchez, Darte & Rastello 2007, p. 103.
  10. Colombet, Brandner & Darte 2011, p. 26.
  11. "Intel® 64 and IA-32 Architectures Software Developer's Manual, Section 3.4.1" (PDF).
  12. "32-bit PowerPC function calling conventions".
  13. Bouchez, Darte & Rastello 2006, p. 4.
  14. Horwitz et al. 1966, p. 43.
  15. Farach & Liberatore 1998, p. 566.
  16. Eisl et al. 2017, p. 92.
  17. Eisl et al. 2018, p. 1.
  18. Briggs, Cooper & Torczon 1992, p. 316.
  19. Chaitin et al., p. 47.
  20. Poletto & Sarkar 1999, p. 896.
  21. Runeson & Nyström 2003, p. 241.
  22. Book 1972, p. 618-619.
  23. Colombet et al. 2011, p. 1.
  24. Smith & Ramsey 2004, p. 277.
  25. Cavazos & Moss 2006, p. 124.
  26. Runeson & Nyström 2003, p. 240.
  27. Poletto & Sarkar 1999, p. 895.
  28. Poletto & Sarkar 1999, p. 902.
  29. Wimmer & Mössenböck 2005, p. 132.
  30. Johansson & Sagonas 2002, p. 102.
  31. Poletto & Sarkar 1999, p. 899.
  32. Eisl et al. 2016, p. 2.
  33. Traub, Holloway & Smith 1998, p. 143.
  34. Traub, Holloway & Smith 1998, p. 141.
  35. Poletto & Sarkar 1999, p. 897.
  36. Wimmer & Franz 2010, p. 170.
  37. Mössenböck & Pfeiffer 2002, p. 234.
  38. Mössenböck & Pfeiffer 2002, p. 233.
  39. Mössenböck & Pfeiffer 2002, p. 229.
  40. Briggs, Cooper & Torczon 1992, p. 313.
  41. Chaitin 1982, p. 90.
  42. Ahn & Paek 2009, p. 7.
  43. Park & Moon 2004, p. 736.
  44. Chaitin 1982, p. 99.
  45. Park & Moon 2004, p. 738.
  46. Briggs, Cooper & Torczon 1994, p. 433.
  47. George & Appel 1996, p. 212.
  48. Park & Moon 2004, p. 741.
  49. Eisl & Marr 2017, p. 11.
  50. Cavazos & Moss 2006, p. 124-127.
  51. Eisl et al. 2016, p. 4.
  52. Diouf, Cohen & Rastello 2010, p. 66.
  53. Cohen & Rohou 2010, p. 1.
  54. Diouf, Cohen & Rastello 2010, p. 72.
  55. Bouchez, Darte & Rastello 2007, p. 1.
  56. Poletto & Sarkar 1999, p. 901-910.
  57. Blackburn et al., p. 169.
  58. Flajolet, Raoult & Vuillemin 1979.


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