PWRficient is the name of a series of microprocessors designed by P.A. Semi where the PA6T-1682M was the only one that became an actual product.

PWRficient processors comply with the 64-bit Power ISA, and are designed for high performance and extreme power efficiency. The processors are highly modular and can be combined to multi-core system-on-a-chip designs, combining CPU, northbridge, and southbridge functionality on a single processor die.

The PA6T was the first and only processor core from P.A. Semi, and it was offered in two distinct lines of products, 16xxM dual core processors and 13xxM/E single core processors. The PA6T lines differed in their L2 cache size, their memory controllers, their communication functionality, and their cryptography offloading features. At one time, P.A. Semi had plans to offer parts with up to 16 cores.[1]

The PA6T core is the first Power ISA core to be designed from scratch outside the AIM alliance (i.e. not designed by IBM, Motorola/Freescale, or Apple Inc.) in ten years. Since Texas Instruments was one of the investors in P.A. Semi, it was suggested that their fabrication plants would have been used to manufacture the PWRficient processors.[1]

PWRficient processors were initially shipped to select customers in February 2007 and were released for worldwide sale in Q4 2007.[2]

P.A. Semi was bought by Apple Inc. in April 2008,[3] and closed down development of PWRficient architecture processors. However, it will continue to manufacture, sell and support these components for the foreseeable future due to an agreement with the US Government, as the processors are used in some military applications.[4][5]


General Info
Designed byP.A. Semi
Max. CPU clock rate1.8 GHz to 2.0 GHz
L1 cache64+64 KB/core
L2 cache2 MB/core
Architecture and classification
Min. feature size65 nm
Instruction setPower ISA (Power ISA v.2.04)
Physical specifications
  • 2

PWRficient processors comprise three parts:



Memory system


  • scalable cross-bar interconnect
  • 1–8 SMP cores
  • 1–2 L2 caches, 512 KB – 8 MB large. 16 GB/s bandwidth.
  • 1–4 1067 MHz DDR2 memory controllers. 16 GB/s bandwidth.
  • 64 GB/s peak bandwidth
  • MOESI coherency



Notable users


  1. "PA Semi heads to 16 cores on back of $50m boost". The Register. 2006-05-17. Retrieved 2012-07-02. External link in |publisher= (help)
  2. "Press release". P.A. Semi. Archived from the original on August 21, 2007. Retrieved 2007-02-07.
  3. Brown, Erika; Corcoran, Elizabeth; Caulfield, Brian (2008-04-23). "Apple Buys Chip Designer". Forbes. Retrieved 2011-07-05.
  4. "Apple will please missile makers by backing PA Semi's chip". The Register. 2008-05-16. Retrieved 2011-07-05.
  5. "DoD may push back on Apple's P.A. Semi bid". EETimes. 2008-05-23. Retrieved 2011-07-05.
  7. Missing or empty |title= (help)
  9. "Archived copy". Archived from the original on 2011-07-07. Retrieved 2011-07-05.CS1 maint: archived copy as title (link)
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