Motorola 88110

The MC88110 was a microprocessor developed by Motorola that implemented the 88000 instruction set architecture (ISA). The MC88110 was a second-generation implementation of the 88000 ISA, succeeding the MC88100. It was designed for use in personal computers and workstations.


The first technical description of the MC88110 was given in November 1991 at the Microprocessor Forum held in San Francisco. The microprocessor was introduced in 1992, operating at 50 MHz. Users were Data General in their AViiON servers, Harris in real-time UNIX systems and Motorola in their single-board computers. NeXT was to introduce a workstation using the MC88110, the NeXT RISC Workstation, but they left the hardware business and cancelled the product before development had completed.


It implemented extensions to the original ISA, such a separate floating-point register file, extended-precision (80-bit) floating-point data types and new integer and graphics instructions. It also implemented microarchitectural features previously non-existent in 88000 microprocessors, such as two-way superscalar execution, out-of-order completion and speculative execution. Despite these new features, which corrected some architectural deficiencies in the MC88100, the MC88110 was ultimately unsuccessful and was used in few systems. The MC88110 was succeeded by PowerPC microprocessors Motorola developed jointly with International Business Machines (IBM) as part of the AIM alliance, but remained available until the mid-1990s.

The MC88110 supported an optional external 256 KB to 2 MB secondary cache. The secondary cache controller was not integrated on the MC88110, but was located on a separate device, the MC88410, to reduce cost.

The die contained 1.3 million transistors and measured 15 mm by 15 mm (225 mm2). It was fabricated in a 1 µm complementary metal–oxide–semiconductor (CMOS) process. The process has three levels of aluminium interconnect and an effective channel length (the distance between the source and drain contacts of the MOSFET transistors) of 0.8 µm. The MC88110 was designed to be shrunk to a 0.8 µm process with an effective channel length of 0.65 µm without modification.


  • Diefendorff, Keith; Allen, Michael (April 1992). "Organization of the Motorola 88110 Superscalar RISC Microprocessor". IEEE Micro. pp. 4063.
  • Tabak, Daniel (1995). Advance Microprocessors (2 ed.). McGraw-Hill. pp. 425–435.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.