Heterogeneous computing refers to systems that use more than one kind of processor or cores. These systems gain performance or energy efficiency not just by adding the same type of processors, but by adding dissimilar coprocessors, usually incorporating specialized processing capabilities to handle particular tasks.
Usually heterogeneity in the context of computing referred to different instruction-set architectures (ISA), where the main processor has one and other processors have another - usually a very different - architecture (maybe more than one), not just a different microarchitecture (floating point number processing is a special case of this - not usually referred to as heterogeneous). For example, ARM big.LITTLE is an exception where the ISAs of cores are the same and heterogeneity refers to the speed of different microarchitectures of the same ISA, thus making it more like a symmetric multiprocessor (SMP).
In the past heterogeneous computing meant different ISAs had to be handled differently, while in a modern example, Heterogeneous System Architecture (HSA) systems eliminate the difference (for the user) while using multiple processor types (typically CPUs and GPUs), usually on the same integrated circuit, to provide the best of both worlds: general GPU processing (apart from the GPU's well-known 3D graphics rendering capabilities, it can also perform mathematically intensive computations on very large data-sets), while CPUs can run the operating system and perform traditional serial tasks.
The level of heterogeneity in modern computing systems is gradually increasing as further scaling of fabrication technologies allows for formerly discrete components to become integrated parts of a system-on-chip, or SoC. For example, many new processors now include built-in logic for interfacing with other devices (SATA, PCI, Ethernet, USB, RFID, radios, UARTs, and memory controllers), as well as programmable functional units and hardware accelerators (GPUs, cryptography co-processors, programmable network processors, A/V encoders/decoders, etc.).
Recent findings show that a heterogeneous-ISA chip multiprocessor that exploits diversity offered by multiple ISAs, can outperform the best same-ISA homogeneous architecture by as much as 21% with 23% energy savings and a reduction of 32% in Energy Delay Product (EDP). AMD's 2014 announcement on its pin-compatible ARM and x86 SoCs, codename Project Skybridge, suggested a heterogeneous-ISA (ARM+x86) chip multiprocessor in the making.
Heterogeneous computing systems present new challenges not found in typical homogeneous systems. The presence of multiple processing elements raises all of the issues involved with homogeneous parallel processing systems, while the level of heterogeneity in the system can introduce non-uniformity in system development, programming practices, and overall system capability. Areas of heterogeneity can include:
- ISA or instruction-set architecture
- Compute elements may have different instruction set architectures, leading to binary incompatibility.
- ABI or application binary interface
- API or application programming interface
- Low-Level Implementation of Language Features
- Language features such as functions and threads are often implemented using function pointers, a mechanism which requires additional translation or abstraction when used in heterogeneous environments.
- Memory Interface and Hierarchy
- Compute elements may have different cache structures, cache coherency protocols, and memory access may be uniform or non-uniform memory access (NUMA). Differences can also be found in the ability to read arbitrary data lengths as some processors/units can only perform byte-, word-, or burst accesses.
- Compute elements may have differing types of interconnect aside from basic memory/bus interfaces. This may include dedicated network interfaces, Direct memory access (DMA) devices, mailboxes, FIFOs, and scratchpad memories, etc. Furthermore, certain portions of a heterogeneous system may be cache-coherent, whereas others may require explicit software-involvement for maintaining consistency and coherency.
- A heterogeneous system may have CPUs that are identical in terms of architecture, but have underlying micro-architectural differences that lead to various levels of performance and power consumption. Asymmetries in capabilities paired with opaque programming models and operating system abstractions can sometimes lead to performance predictability problems, especially with mixed workloads.
- Data Partitioning
Heterogeneous computing platforms can be found in every domain of computing—from high-end servers and high-performance computing machines all the way down to low-power embedded devices including mobile phones and tablets.
- High Performance Computing
- Embedded Systems (DSP and Mobile Platforms)
- Texas Instruments OMAP
- Analog Devices Blackfin
- Qualcomm Snapdragon
- Nvidia Tegra
- Samsung Exynos
- Apple "A" series
- Movidius Myriad Vision processing units, which includes several symmetric processors, complemented by fixed function units, and a pair of SPARC based controllers.
- HiSilicon Kirin SoCs
- MediaTek SoCs
- Cadence Design Systems Tensilica DSPs
- Reconfigurable Computing
- Intel IXP Network Processors
- Netronome NFP Network Processors
- General Purpose Computing, Gaming, and Entertainment Devices
- Intel Sandy Bridge, Ivy Bridge, and Haswell CPUs
- AMD Excavator and Ryzen APUs
- IBM Cell, found in the PlayStation 3
- SpursEngine, a variant of the IBM Cell processor
- Emotion Engine, found in the PlayStation 2
- ARM big.LITTLE/DynamIQ CPU architecture
- Nearly all ARM vendors offer heterogeneous solutions; ARM, Qualcomm, Nvidia, Apple, Samsung, HiSilicon, MediaTek, etc.
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- Venkat, Ashish; Tullsen, Dean M. (2014). Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor. Proceedings of the 41st Annual International Symposium on Computer Architecture.
Anand Lal Shimpi (2014-05-05). "AMD Announces Project SkyBridge: Pin-Compatible ARM and x86 SoCs in 2015, Android Support". AnandTech. Retrieved 2017-06-11.
Next year, AMD will release a low-power 20nm Cortex A57 based SoC with integrated Graphics Core Next GPU.
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- Beaumont, Olivier; Becker, Brett; DeFlumere, Ashley; Eyraud-Dubois, Lionel; Lastovetsky, Alexey (July 2018). "Recent Advances in Matrix Partitioning for Parallel Computing on Heterogeneous Platforms" (PDF). IEEE Transactions on Parallel and Distributed Computing.
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