Extended Display Identification Data

Extended Display Identification Data (EDID) is a metadata format for display devices to describe their capabilities to a video source (e.g. graphics card or set-top box). The data format is defined by a standard published by the Video Electronics Standards Association (VESA).

The EDID data structure includes manufacturer name and serial number, product type, phosphor or filter type, timings supported by the display, display size, luminance data and (for digital displays only) pixel mapping data.

DisplayID is a VESA standard targeted to replace EDID and E-EDID extensions with a uniform format suited for both PC monitor and consumer electronics devices.


EDID structure versions range from v1.0 to v1.4; all these define upwards-compatible 128-byte structures. Version 2.0 defined a new 256-byte structure but it has been deprecated and replaced by v1.3 which supports multiple extension blocks. HDMI versions 1.0–1.3c use EDID structure v1.3.[1]

Before Display Data Channel (DDC) and EDID were defined, there was no standard way for a graphics card to know what kind of display device it was connected to. Some VGA connectors in personal computers provided a basic form of identification by connecting one, two or three pins to ground, but this coding was not standardized.

The channel for transmitting the EDID from the display to the graphics card is usually the I²C-bus, defined in DDC2B (DDC1 used a different serial format which never gained popularity).

The EDID is often stored in the monitor in a memory device called a serial PROM (programmable read-only memory) or EEPROM (electrically erasable PROM) and is accessible via the I²C-bus at address A0. The EDID PROM can often be read by the host PC even if the display itself is turned off.

Many software packages can read and display the EDID information, such as read-edid[2] for Linux and DOS, PowerStrip[3] for Microsoft Windows and XFree86 for Linux and BSD unix. Mac OS X natively reads EDID information and programs such as SwitchResX[4] or DisplayConfigX[5] can display the information as well as use it to define custom resolutions.

Enhanced EDID was introduced at the same time as E-DDC; it introduced EDID structure version 1.3 which supports multiple extensions blocks and deprecated EDID version 2.0 structure (although it can be supported as an extension). Data fields for preferred timing, range limits, and monitor name are required in E-EDID. E-EDID also supports dual GTF timings and aspect ratio change.

With the use of extensions, E-EDID string can be lengthened up to 32 KBytes.

EDID Extensions assigned by VESA

  • Timing Extension (00)
  • Additional Timing Data Block (CEA EDID Timing Extension) (02)
  • Video Timing Block Extension (VTB-EXT) (10)
  • EDID 2.0 Extension (20)
  • Display Information Extension (DI-EXT) (40)
  • Localized String Extension (LS-EXT) (50)
  • Microdisplay Interface Extension (MI-EXT) (60)
  • Display ID Extension (70)
  • Display Transfer Characteristics Data Block (DTCDB) (A7, AF, BF)
  • Block Map (F0)
  • Display Device Data Block (DDDB) (FF)
  • Extension defined by monitor manufacturer (FF): According to LS-EXT, actual contents varies from manufacturer. However, the value is later used by DDDB.

Revision history

  • August 1994, DDC standard version 1 – EDID v1.0 structure.
  • April 1996, EDID standard version 2 – EDID v1.1 structure.
  • 1997, EDID standard version 3 – EDID structures v1.2 and v2.0
  • February 2000, E-EDID Standard Release A, v1.0 – EDID structure v1.3, EDID structure v2.0 deprecated
  • September 2006 – E-EDID Standard Release A, v2.0 – EDID structure v1.4


Some graphics card drivers have historically coped poorly with the EDID, using only its standard timing descriptors rather than its Detailed Timing Descriptors (DTDs). Even in cases where the DTDs were read, the drivers are/were still often limited by the standard timing descriptor limitation that the horizontal/vertical resolutions must be evenly divisible by 8. This means that many graphics cards cannot express the native resolutions of the most common wide screen flat panel displays and liquid crystal display televisions. The number of vertical pixels is calculated from the horizontal resolution and the selected aspect ratio. To be fully expressible, the size of wide screen display must thus be a multiple of 16×9 pixels. For 1366×768 pixel Wide XGA panels the nearest resolution expressible in the EDID standard timing descriptor syntax is 1360×765 pixels, typically leading to 3 pixel thin black bars. Specifying 1368 pixels as the screen width would yield an unnatural screen height of 769.5 pixels.

Many Wide XGA panels do not advertise their native resolution in the standard timing descriptors, instead offering only a resolution of 1280×768. Some panels advertise a resolution only slightly smaller than the native, such as 1360×765. For these panels to be able to show a pixel perfect image, the EDID data must be ignored by the display driver or the driver must correctly interpret the DTD and be able to resolve resolutions whose size is not divisible by 8. Special programs are available to override the standard timing descriptors from EDID data. Even this is not always possible, as some vendors' graphics drivers (notably those of Intel) require specific registry hacks to implement custom resolutions, which can make it very difficult to use the screen's native resolution.[6]

EDID 1.4 data format

Structure, version 1.4

EDID structure, version 1.4[7][8]
0–19Header information
0–7Fixed header pattern: 00 FF FF FF FF FF FF 00
8–9Manufacturer ID. This is a legacy Plug and Play ID assigned by Microsoft, which is a big-endian 16-bit value made up of three 5-bit letters: 00001, A; 00010, B; …; 11010, Z. E.g., 24 4d, 0 01001 00010 01101, "IBM".
Bit 15Reserved, always 0
Bits 14–10First letter of manufacturer ID (byte 8, bits 6–2)
Bits 9–5Second letter of manufacturer ID (byte 8, bit 1 through byte 9 bit 5)
Bits 4–0Third letter of manufacturer ID (byte 9 bits 4–0)
10–11Manufacturer product code. 16-bit number, little-endian.
12–15Serial number. 32 bits, little-endian.
16Week of manufacture; or FF model year flag. Week numbering is not consistent between manufacturers.
17Year of manufacture, or year of model, if model year flag is set. Year = datavalue + 1990.
18EDID version, usually 01 (for 1.3 and 1.4)
19EDID revision, usually 03 (for 1.3) or 04 (for 1.4)
20–24Basic display parameters
20Video input parameters bitmap
Bit 7, 1Digital input. If set, the following bit definitions apply:
Bits 6–4Bit depth: 000, undefined; 001, 6; 010, 8; 011, 10; 100, 12; 101, 14; 110, 16 bits per color; 111, reserved.
Bits 3–0Video interface: 0000, undefined; 0010, HDMIa; 0011, HDMIb; 0100, MDDI; 0101, DisplayPort.
Bit 7, 0Analog input. If clear, the following bit definitions apply:
Bits 6–5Video white and sync levels, relative to blank: 00, +0.7/−0.3 V; 01, +0.714/−0.286 V; 10, +1.0/−0.4 V; 11, +0.7/0 V.
Bit 4Blank-to-black setup (pedestal) expected
Bit 3Separate sync supported
Bit 2Composite sync (on HSync) supported
Bit 1Sync on green supported
Bit 0VSync pulse must be serrated when composite or sync-on-green is used.
21Horizontal screen size, in centimetres (range 1–255). If vertical screen size is 0, landscape aspect ratio (range 1.00–3.54), datavalue = (AR×100) − 99 (example: 16:9, 79; 4:3, 34.)
22Vertical screen size, in centimetres. If horizontal screen size is 0, portrait aspect ratio (range 0.28–0.99), datavalue = (100/AR) − 99 (example: 9:16, 79; 3:4, 34.) If either byte is 0, screen size and aspect ratio are undefined (e.g. projector)
23Display gamma, factory default (range 1.00–3.54), datavalue = (gamma×100) − 100 = (gamma − 1)×100. If 225, gamma is defined by DI-EXT block.
24Supported features bitmap
Bit 7DPMS standby supported
Bit 6DPMS suspend supported
Bit 5DPMS active-off supported
Bits 4–3 Display type (digital): 00, RGB 4:4:4; 01, RGB 4:4:4 + YCrCb 4:4:4; 10, RGB 4:4:4 + YCrCb 4:2:2; 11, RGB 4:4:4 + YCrCb 4:4:4 + YCrCb 4:2:2
Display type (analog): 00, monochrome or grayscale; 01, RGB color; 10, non-RGB color; 11, undefined.
Bit 2Standard sRGB colour space. Bytes 25–34 must contain sRGB standard values.
Bit 1Preferred timing mode specified in descriptor block 1. For EDID 1.3+ the preferred timing mode is always in the first Detailed Timing Descriptor. In that case, this bit specifies whether the preferred timing mode includes native pixel format and refresh rate.
Bit 0Continuous timings with GTF or CVT
25–34Chromaticity coordinates.
10-bit CIE 1931 xy coordinates for red, green, blue, and white point
25Red and green least-significant bits (2−9, 2−10)
Bits 7–6Red x value least-significant 2 bits
Bits 5–4Red y value least-significant 2 bits
Bits 3–2Green x value least-significant 2 bits
Bits 1–0Green y value least-significant 2 bits
26Blue and white least-significant 2 bits
27Red x value most significant 8 bits (2−1, …, 2−8). 0–255 encodes fractional 0–0.996 (255/256); 0–0.999 (1023/1024) with lsbits
28Red y value most significant 8 bits
29–30Green x and y value most significant 8 bits
31–32Blue x and y value most significant 8 bits
33–34Default white point x and y value most significant 8 bits
35–37Established timing bitmap. Supported bitmap for (formerly) very common timing modes.
35Bit 7720×400 @ 70 Hz (VGA)
Bit 6720×400 @ 88 Hz (XGA)
Bit 5640×480 @ 60 Hz (VGA)
Bit 4640×480 @ 67 Hz (Apple Macintosh II)
Bit 3640×480 @ 72 Hz
Bit 2640×480 @ 75 Hz
Bit 1800×600 @ 56 Hz
Bit 0800×600 @ 60 Hz
36Bit 7800×600 @ 72 Hz
Bit 6800×600 @ 75 Hz
Bit 5832×624 @ 75 Hz (Apple Macintosh II)
Bit 41024×768 @ 87 Hz, interlaced (1024×768i)
Bit 31024×768 @ 60 Hz
Bit 21024×768 @ 70 Hz
Bit 11024×768 @ 75 Hz
Bit 01280×1024 @ 75 Hz
37Bit 71152x870 @ 75 Hz (Apple Macintosh II)
Bits 6–0Other manufacturer-specific display modes
38–53Standard timing information. Up to 8 2-byte fields describing standard display modes.
Unused fields are filled with 01 01. The following definitions apply in each record:
0X resolution, 00, reserved; otherwise, (datavalue + 31) × 8 (256–2288 pixels).
1 Bits 7–6Image aspect ratio: 00, 16:10; 01, 4:3; 10, 5:4; 11, 16:9. (Versions prior to 1.3 defined 00 as 1:1.)
Bits 5–0Vertical frequency, datavalue + 60 (60–123 Hz)
54–71Descriptor 118 byte descriptors. Detailed timing descriptors, in decreasing preference order, followed by display descriptors:
  • Monitor range limits (required)
  • ASCII text (monitor name (required), monitor serial number or unstructured text)
  • 6 additional standard timing information blocks
  • Colour point data
72–89Descriptor 2
90–107Descriptor 3
108–125Descriptor 4
126Number of extensions to follow. 0 if no extensions.
127Checksum. Sum of all 128 bytes should equal 0 (mod 256).

Detailed Timing Descriptor

EDID Detailed Timing Descriptor[7]
0–1Pixel clock. 00, reserved; otherwise in 10 kHz units (0.01–655.35 MHz, little-endian).
2Horizontal active pixels 8 lsbits (0–4095)
3Horizontal blanking pixels 8 lsbits (0–4095) End of active to start of next active.
4Bits 7–4Horizontal active pixels 4 msbits
Bits 3–0Horizontal blanking pixels 4 msbits
5Vertical active lines 8 lsbits (0–4095)
6Vertical blanking lines 8 lsbits (0–4095)
7Bits 7–4Vertical active lines 4 msbits
Bits 3–0Vertical blanking lines 4 msbits
8Horizontal front porch (sync offset) pixels 8 lsbits (0–1023) From blanking start
9Horizontal sync pulse width pixels 8 lsbits (0–1023)
10Bits 7–4Vertical front porch (sync offset) lines 4 lsbits (0–63)
Bits 3–0Vertical sync pulse width lines 4 lsbits (0–63)
11Bits 7–6Horizontal front porch (sync offset) pixels 2 msbits
Bits 5–4Horizontal sync pulse width pixels 2 msbits
Bits 3–2Vertical front porch (sync offset) lines 2 msbits
Bits 1–0Vertical sync pulse width lines 2 msbits
12Horizontal image size, mm, 8 lsbits (0–4095 mm, 161 in)
13Vertical image size, mm, 8 lsbits (0–4095 mm, 161 in)
14Bits 7–4Horizontal image size, mm, 4 msbits
Bits 3–0Vertical image size, mm, 4 msbits
15Horizontal border pixels (one side; total is twice this)
16Vertical border lines (one side; total is twice this)
17Features bitmap
Bit 7Interlaced
Bits 6–5, 0Stereo mode:
  • 00, none, bit 0 is reserved;
  • 01 0, field sequential, right during stereo sync;
  • 10 0, field sequential, left during stereo sync;
  • 01 1, 2-way interleaved, right image on even lines;
  • 10 1, 2-way interleaved, left image on even lines;
  • 11 0, 4-way interleaved;
  • 11 1, side-by-side interleaved.
Bit 4, 0Analog sync.
If set, the following bit definitions apply:
Bit 3Sync type: 0, analog composite; 1, bipolar analog composite.
Bit 2VSync serration (HSync during VSync)
Bit 1Sync on red and blue lines additionally to green
Bits 4–3, 10Digital sync., composite (on HSync).
If set, the following bit definitions apply:
Bit 2Vertical sync polarity (0, negative; 1, positive.)
Bit 1Reserved
Bits 4–3, 11Digital sync., separate
If set, the following bit definitions apply:
Bit 2VSync serration (HSync during VSync)
Bit 1Horizontal sync polarity (0, negative; 1, positive;)

When used for another descriptor, the pixel clock and some other bytes are set to 0:

Display Descriptors

EDID Display Descriptors[7]
0–1 0, indicates Display Descriptor (cf. Detailed Timing Descriptor).
20, reserved
3Descriptor type. FAFF currently defined. 000F reserved for vendors.
40, reserved, except for Display Range Limits Descriptor.
5–17Defined by descriptor type. If text, code page 437 text, terminated (if less than 13 bytes) with LF and padded with SP.

Currently defined descriptor types are:

  • FF: Display serial number (ASCII text)
  • FE: Unspecified text (ASCII text)
  • FD: Display range limits. 6- or 13-byte (with additional timing) binary descriptor.
  • FC: Display name (ASCII text).
  • FB: Additional white point data. 2× 5-byte descriptors, padded with 0A 20 20.
  • FA: Additional standard timing identifiers. 6× 2-byte descriptors, padded with 0A.
  • F9: Display Color Management (DCM).
  • F8: CVT 3-Byte Timing Codes.
  • F7: Additional standard timing 3.
  • 10: Dummy identifier.
  • 00–0F: Manufacturer reserved descriptors.

Display Range Limits


EDID Display Range Limits Descriptor[7]
0–100 00, Display Descriptor
200, reserved
3FD, Display Range Limits Descriptor
4 Offsets for display range limits
Bits 7–4Unused, must be 0.
Bits 3–2Horizontal rate offsets: 00, none; 10, +255 kHz for max. rate; 11, +255 kHz for max. and min. rates.
Bits 1–0Vertical rate offsets: 00, none; 10, +255 Hz for max. rate; 11, +255 Hz for max. and min. rates.
5Minimum vertical field rate (1–255 Hz; 256–512 Hz, if offset).
6Maximum vertical field rate (1–255 Hz; 256–512 Hz, if offset).
7Minimum horizontal line rate (1–255 kHz; 256–512 kHz, if offset).
8Maximum horizontal line rate (1–255 kHz; 256–512 kHz, if offset).
9Maximum pixel clock rate, rounded up to 10 MHz multiple (10–2550 MHz).
10Extended timing information type:
  • 00: Default GTF (when basic display parameters byte 24, bit 0 is set.
  • 01: No timing information.
  • 02: Secondary GTF supported, parameters as follows.
  • 04: CVT (when basic display parameters byte 24, bit 0 is set), parameters as follows.
11–17Video timing parameters (if byte 10 is 00 or 01, padded with 0A 20 20 20 20 20 20).

With GTF secondary curve

EDID Display Range Limits with GTF Secondary curve[7]
11Reserved, must be 0.
12Start frequency for secondary curve, divided by 2 kHz (0–510 kHz)
13GTF C value, multiplied by 2 (0–127.5)
14–15GTF M value (0–65535, little-endian)
16GTF K value (0–255)
17GTF J value, multiplied by 2 (0–127.5)

With CVT support

EDID Display Range Limits with CVT support[7]
11Bits 7–4CVT major version (1–15)
Bits 3–0CVT minor version (0–15)
12Bits 7–2Additional clock precision in 0.25 MHz increments
(to be subtracted from byte 9 maximum pixel clock rate)
Bits 1–0Maximum active pixels per line, 2-bit msb
13Maximum active pixels per line, 8-bit lsb (no limit if 0)
14Aspect ratio bitmap
Bit 74:3
Bit 616:9
Bit 516:10
Bit 45:4
Bit 315:9
Bits 2–0Reserved, must be 0.
15Bits 7–5Aspect ratio preference: 000, 4:3; 001, 16:9; 010, 16:10; 011, 5:4; 100, 15:9.
Bit 4CVT-RB reduced blanking (preferred)
Bit 3CVT standard blanking
Bits 2–0Reserved, must be 0.
16Scaling support bitmap
Bit 7Horizontal shrink
Bit 6Horizontal stretch
Bit 5Vertical shrink
Bit 4Vertical stretch
Bits 3–0Reserved, must be 0.
17Preferred vertical refresh rate (1–255)

Additional white point descriptor

EDID additional white point descriptor[7]
0–4Standard header, byte 3, FB.
5White point index number (1–255). Usually 1; 0 indicates descriptor not used.
6White point CIE xy coordinates least-significant bits (like EDID byte 26)
Bits 7–4Unused, must be 0.
Bits 3–2White point x value least-significant 2 bits
Bits 1–0White point y value least-significant 2 bits
7White point x value most significant 8 bits (like EDID byte 27)
8White point y value most significant 8 bits (like EDID byte 28)
9datavalue = (gamma − 1)×100 (1.0–3.54, like EDID byte 23)
10–14Second descriptor, like above. Index number usually 2.
15–17Unused, padded with 0A 20 20.

Color management data descriptor

EDID color management data descriptor[7]
0–4Standard header: byte 3, F9.
5Version: 03
6Red a3 lsb
7Red a3 msb
8Red a2 lsb
9Red a2 msb
10Green a3 lsb
11Green a3 msb
12Green a2 lsb
13Green a2 msb
14Blue a3 lsb
15Blue a3 msb
16Blue a2 lsb
17Blue a2 msb

CVT 3-byte timing codes descriptor

EDID CVT 3-byte timing codes descriptor[7]
0–4Standard header: byte 3, F8.
5Version: 01
6-8CVT timing descriptor #1
6Addressable lines 8-bit lsb
7Bits 7–4Addressable lines 4-bit msb
Bits 3–2Aspect ratio: 00, 4:3; 01, 16:9; 10, 16:10; 11, 15:9.
Bits 1–0Unused, must be 0.
8Bit 7Unused, must be 0.
Bits 6–5Preferred vertical rate: 00, 50 Hz; 01, 60 Hz; 10, 75 Hz; 11, 85 Hz.
Vertical rate bitmap
Bit 450 Hz CVT
Bit 360 Hz CVT
Bit 275 Hz CVT
Bit 185 Hz CVT
Bit 060 Hz CVT reduced blanking
9–11CVT timing descriptor #2
12–14CVT timing descriptor #3
15–17CVT timing descriptor #4

Additional standard timings

EDID Additional standard timings 3[7]
0–4Standard header: byte 3, F7.
5Version: 10
6Bit 7640×350 @ 85 Hz
Bit 6640×400 @ 85 Hz
Bit 5720×400 @ 85 Hz
Bit 4640×480 @ 85 Hz
Bit 3848×480 @ 60 Hz
Bit 2800×600 @ 85 Hz
Bit 11024×768 @ 85 Hz,
Bit 01152×864 @ 85 Hz
7Bit 71280×768 @ 60 Hz (CVT-RB)
Bit 61280×768 @ 60 Hz
Bit 51280×768 @ 75 Hz
Bit 41280×768 @ 85 Hz
Bit 31280×960 @ 60 Hz
Bit 21280×960 @ 85 Hz
Bit 11280×1024 @ 60 Hz
Bit 01280×1024 @ 85 Hz
8Bit 71360×768 @ 60 Hz (CVT-RB)
Bit 61280×768 @ 60 Hz
Bit 51440×900 @ 60 Hz (CVT-RB)
Bit 41440×900 @ 75 Hz
Bit 31440×900 @ 85 Hz
Bit 21440×1050 @ 60 Hz (CVT-RB)
Bit 11440×1050 @ 60 Hz
Bit 01440×1050 @ 75 Hz
9Bit 71440×1050 @ 85 Hz
Bit 61680×1050 @ 60 Hz (CVT-RB)
Bit 51680×1050 @ 60 Hz
Bit 41680×1050 @ 75 Hz
Bit 31680×1050 @ 85 Hz
Bit 21600×1200 @ 60 Hz
Bit 11600×1200 @ 65 Hz
Bit 01600×1200 @ 70 Hz
10Bit 71600×1200 @ 75 Hz
Bit 61600×1200 @ 85 Hz
Bit 51792×1344 @ 60 Hz
Bit 41792×1344 @ 75 Hz
Bit 31856×1392 @ 60 Hz
Bit 21856×1392 @ 75 Hz
Bit 11920×1200 @ 60 Hz (CVT-RB)
Bit 01920×1200 @ 60 Hz
11Bit 71920×1200 @ 75 Hz
Bit 61920×1200 @ 85 Hz
Bit 51920×1440 @ 60 Hz
Bit 41920×1440 @ 75 Hz
Bits 3–0Unused, must be 0.
12–17Unused, must be 0.

EIA/CEA-861 extension block

The CEA EDID Timing Extension was first introduced in EIA/CEA-861, and has since been updated several times, most notably with the −861B revision (which was version 3 of the extension, adding Short Video Descriptors and advanced audio capability/configuration information), −861D (published in July 2006 and containing updates to the audio segments), −861E, and −861F which was published on June 4, 2013.[9] According to Brian Markwalter, senior vice president, research and standards, CEA, −861F "includes a number of noteworthy enhancements, including support for several new Ultra HD and widescreen video formats and additional colorimetry schemes.”[10]

The most recent version, CTA-861-G,[11] originally published in November 2016, was made available for free in November 2017 after some necessary changes due to a trademark complaint.

Version 1 (as defined in −861) allowed the specification of video timings only through the use of 18-byte Detailed Timing Descriptors (DTD) (as detailed in EDID 1.3 data format above). In all cases, the "preferred" timing should be the first DTD listed in a CEA EDID Timing Extension.

Version 2 (as defined in −861A) added the capability to designate a number of DTDs as "native" and also included some "basic discovery" functionality for whether the display device contains support for "basic audio", YCbCr pixel formats, and underscan.

Version 3 (from the −861B spec) allows two different ways to specify the timings of available digital TV formats: As in Version 1 & 2 by the use of 18-byte DTDs, or by the use of the Short Video Descriptor (SVD) (see below). HDMI 1.0–1.3c uses this version.

Version 3 also includes four new optional types of data blocks: Video Data Blocks containing the aforementioned Short Video Descriptor (SVD), Audio Data Blocks containing Short Audio Descriptors (SAD), Speaker Allocation Data Blocks containing information about the speaker configuration of the display device, and Vendor Specific Data Blocks which can contain information specific to a given vendor's use.

CEA EDID Timing Extension data format - Version 3

Byte Description
0 Extension tag (which kind of extension block this is); 02 for CEA EDID
1 Revision number (version number); 03 for version 3
2 Byte number (decimal) within this block where the 18-byte DTDs begin. If no non-DTD data is present in this extension block, the value should be set to 04 (the byte after next). If set to 00, there are no DTDs present in this block and no non-DTD data.
3 Number of Native DTDs present, other version 2+ information
Bit 71 if display supports underscan, 0 if not
Bit 61 if display supports basic audio, 0 if not
Bit 51 if display supports YCbCr 4:4:4, 0 if not
Bit 41 if display supports YCbCr 4:2:2, 0 if not
Bit 3–0Total number of native formats in the DTDs included in this block
4–126 Data Block Collection, starting at byte 4, ending immediately before the byte specified in byte 2. If byte 2 is 04, the collection is of zero length (i.e., not present).
18-byte descriptors, starting at the byte specified in byte 2. Consecutive descriptors are present while the bytes 0–1 of each are not 00 00.
Padding, from the absence of an 18-byte descriptor onwards; must be 00.
127 Checksum. Value such that the sum of all 128 bytes is 00.

The Data Block Collection contains one or more data blocks detailing video, audio, and speaker placement information about the display. The blocks can be placed in any order, and the initial byte of each block defines both its type and its length:

Data block header
Byte Description
0 Bit 7–5Block Type Tag. 1, audio; 2, video; 3, vendor specific; 4, speaker allocation; else reserved.
Bit 4–0Total number of bytes in this block following this byte.

Once one data block has ended, the next byte is assumed to be the beginning of the next data block. This is the case until the byte (designated in byte 2, above) where the DTDs are known to begin.

Audio Data Blocks contain one or more 3-byte Short Audio Descriptors (SADs). Each SAD details audio format, channel number, and bitrate/resolution capabilities of the display as follows:

Short Audio Descriptor
Byte Description
0 Data block header
1 Format and number of channels:
Bit 7Reserved, 0
Bit 6–3Audio format code
  • 0, 15: Reserved
  • 1: Linear Pulse Code Modulation (LPCM)
  • 2: AC-3
  • 3: MPEG1 (Layers 1 and 2)
  • 4: MP3
  • 5: MPEG2
  • 6: AAC
  • 7: DTS
  • 8: ATRAC
  • 9: 1-bit audio aka Super Audio CD
  • 10: DD+
  • 11: DTS-HD
  • 12: MLP/Dolby TrueHD
  • 13: DST Audio
  • 14: Microsoft WMA Pro
Bit 2–0Number of channels minus 1 (i.e., 000, 1 channel; 001, 2 channels; 111, 8 channels)
2 Sampling frequencies supported:
Bit 7Reserved, 0
Bit 6192 kHz
Bit 5176 kHz
Bit 496 kHz
Bit 388 kHz
Bit 248 kHz
Bit 144 kHz
Bit 032 kHz
3 Bitrate / format dependent:
For codec 1, LPCM,
Bits 7–3Reserved
Bit 224-bit depth
Bit 120-bit depth
Bit 016-bit depth
For audio format codecs 2–8, the maximum supported bitrate in bit/s, divided by 8000.

Video Data Blocks will contain one or more 1-byte Short Video Descriptors (SVDs).

Byte Description
0 Data block header
1 Bit 71 to designate that this should be considered a "native" resolution, 0 for non-native
Bit 6–0Index value to a table of standard resolutions/timings from EIA/CEA-861:
EIA/CEA-861 standard resolutions and timings
Id. Code)
Aspect ratio Clock Active Total Field
Display Pixel Pixel (MHz) @ Vert. Horiz. H V H V
1DMT06594:31:125.175@59.94 Hz31.469 kHz64048080052560 Hz
2480p4:38:927.0@59.94 Hz31.469 kHz72048085852560 Hz
3480pH16:932:3727.0@59.94 Hz31.469 kHz72048085852560 Hz
4720p16:91:174.25@60 Hz45.0 kHz1280720165075060 Hz
51080i16:91:174.25@60 Hz33.75 kHz19205402200562.560 Hz
6480i4:38:927.0@59.94 Hz15.734 kHz14402401716262.560 Hz
7480iH16:932:3727.0@59.94 Hz15.734 kHz14402401716262.560 Hz
8240p4:34:927.0@59.826 Hz15.734 kHz14402401716262.560 Hz
9240pH16:916:2727.0@59.826 Hz15.734 kHz14402401716262.560 Hz
10480i4x4:32:9-20:954.0@59.94 Hz15.734 kHz28802403432262.560 Hz
11480i4xH16:98:27-80:2754.0@59.94 Hz15.734 kHz28802403432262.560 Hz
12240p4x4:31:9-10:954.0@60 Hz15.734 kHz28802403432262.560 Hz
13240p4xH16:94:27-40:3754.0@60 Hz15.734 kHz28802403432262.560 Hz
14480p2x4:34:9 or 8:954.0@59.94 Hz31.469 kHz1440480171652560 Hz
15480p2xH16:916:27 or 32:3754.0@59.94 Hz31.469 kHz1440480171652560 Hz
161080p16:91:1148.5@60 Hz67.5 kHz192010802200112560 Hz
17576p4:316:1527.0@50 Hz31.25 kHz72057686462550 Hz
18576pH16:964:4527.0@50 Hz31.25 kHz72057686462550 Hz
19720p5016:91:174.25@50 Hz37.5 kHz1280720198075050 Hz
201080i2516:91:174.25@50 Hz28.125 kHz19205402640562.550 Hz
21576i4:316:1527.0@50 Hz15.625 kHz14402881728312.550 Hz
22576iH16:964:4527.0@50 Hz15.625 kHz14402881728312.550 Hz
23288p4:38:1527.0@50 Hz15.625 kHz1440288172831350 Hz
24288pH16:932:4527.0@50 Hz15.625 kHz1440288172831350 Hz
25576i4x4:32:15-20:1554.0@50 Hz15.625 kHz28802883456312.550 Hz
26576i4xH16:916:45-160:4554.0@50 Hz15.625 kHz28802883456312.550 Hz
27288p4x4:31:15-10:1554.0@50 Hz15.625 kHz2880288345631350 Hz
28288p4xH16:98:45-80:4554.0@50 Hz15.625 kHz2880288345631350 Hz
29576p2x4:38:15 or 16:1554.0@50 Hz31.25 kHz1440576172862550 Hz
30576p2xH16:932:45 or 64:4554.0@50 Hz31.25 kHz1440576172862550 Hz
311080p5016:91:1148.5@50 Hz56.25 kHz192010802640112550 Hz
321080p2416:91:174.25@23.98/24 Hz27.0 kHz1920108027501125Low
331080p2516:91:174.25@25 Hz28.125 kHz1920108026401125Low
341080p3016:91:174.25@29.97/30 Hz33.75 kHz1920108025001125Low
35480p4x4:32:9, 4:9 or 8:9108.0@59.94 Hz31.469 kHz28802403432262.560 Hz
36480p4xH16:98:27, 16:27 or 32:27108.0@59.94 Hz31.469 kHz28802403432262.560 Hz
37576p4x4:34:15, 8:15, or 16:15108.0@50 Hz31.25 kHz2880576345662550 Hz
38576p4xH16:916:45, 32:45 or 64:45108.0@50 Hz31.25 kHz2880576345662550 Hz
391080i2516:91:172.0@50 Hz31.25 kHz1920540230462550 Hz
401080i5016:91:1148.5@100 Hz56.25 kHz19205402640562.5100 Hz
41720p10016:91:1148.5@100 Hz45.0 kHz12807201980750100 Hz
42576p1004:316:1554.0@100 Hz62.5 kHz720576864625100 Hz
43576p100H16:964:4554.0@100 Hz62.5 kHz720576864625100 Hz
44576i504:316:1554.0@100 Hz31.25 kHz14405761728625100 Hz
45576i50H16:964:4554.0@100 Hz31.25 kHz14405761728625100 Hz
461080i6016:91:1148.5@119.88/120 Hz67.5 kHz19205402200562.5120 Hz
47720p12016:91:1148.5@119.88/120 Hz90.0 kHz12807201650750120 Hz
48480p1194:38:954.0@119.88/120 Hz62.937 kHz720576858525120 Hz
49480p119H16:932:3754.0@119.88/120 Hz62.937 kHz720576858525120 Hz
50480i594:316:1554.0@119.88/120 Hz31.469 kHz14405761716525120 Hz
51480i59H16:964:4554.0@119.88/120 Hz31.469 kHz14405761716525120 Hz
52576p2004:316:15108.0@200 Hz125.0 kHz720576864625200 Hz
53576p200H16:964:45108.0@200 Hz125.0 kHz720576864625200 Hz
54576i1004:316:15108.0@200 Hz62.5 kHz14402881728312.5200 Hz
55576i100H16:964:45108.0@200 Hz62.5 kHz14402881728312.5200 Hz
56480p2394:38:9108.0@239.76 Hz125.874 kHz720480858525240 Hz
57480p239H16:932:37108.0@239.76 Hz125.874 kHz720480858525240 Hz
58480i1194:38:9108.0@239.76 Hz62.937 kHz14402401716262.5240 Hz
59480i119H16:932:37108.0@239.76 Hz62.937 kHz14402401716262.5240 Hz
60720p2416:91:159.4@23.98/24 Hz18.0 kHz12807203300750Low
61720p2516:91:174.25@25 Hz18.75 kHz12807203960750Low
62720p3016:91:174.25@29.97/30 Hz22.5 kHz12807203300750Low
631080p12016:91:1297.0@119.88/120 Hz135.0 kHz1920108022001125120 Hz
641080p10016:91:1297.0@100 Hz112.5 kHz1920108026401125100 Hz
65720p2464:274:359.4@23.98/24 Hz18.0 kHz12807203300750Low
66720p2564:274:374.25@25 Hz18.75 kHz12807203960750Low
67720p3064:274:374.25@29.97/30 Hz22.5 kHz12807203300750Low
68720p5064:274:374.25@50 Hz37.5 kHz1280720198075050 Hz
69720p64:274:374.25@60 Hz45.0 kHz1650750165075060 Hz
70720p10064:274:3148.5@100 Hz75.0 kHz12807201980750100 Hz
71720p12064:274:3148.5@119.88/120 Hz90.0 kHz12807201650750120 Hz
721080p2464:274:374.25@23.98/24 Hz27.0 kHz1920108027501125Low
731080p2564:274:374.25@25 Hz28.125 kHz1920108026401125Low
741080p3064:274:374.25@29.97/30 Hz33.75 kHz1920108025001125Low
751080p5064:274:3148.5@50 Hz56.25 kHz192010802640112550 Hz
761080p64:274:3148.5@60 Hz67.5 kHz192010802200112560 Hz
771080p10064:274:3297.0@100 Hz112.5 kHz1920108026401125100 Hz
781080p12064:274:3297.0@119.88/120 Hz135.0 kHz1920108022001125120 Hz
79720p2x2464:2764:6359.4@23.98/24 Hz18.0 kHz16807203300750Low
80720p2x2564:2764:6359.4@25 Hz18.75 kHz16807203168750Low
81720p2x3064:2764:6359.4@29.97/30 Hz22.5 kHz16807202640750Low
82720p2x5064:2764:6382.5@50 Hz37.5 kHz1680720220075050 Hz
83720p2x64:2764:6399.0@60 Hz45.0 kHz1680720220075060 Hz
84720p2x10064:2764:63165.0@100 Hz82.5 kHz16807202000825100 Hz
85720p2x12064:2764:63198.0@119.88/120 Hz99.0 kHz16807202000825120 Hz
861080p2x2464:271:199.0@23.98/24 Hz26.4 kHz2560108037501100Low
871080p2x2564:271:190.0@25 Hz28.125 kHz2560108032001125Low
881080p2x3064:271:1118.8@29.97/30 Hz33.75 kHz2560108035201125Low
891080p2x5064:271:1185.625@50 Hz56.25 kHz256010803000112550 Hz
901080p2x64:271:1198.0@60 Hz66.0 kHz256010803000110060 Hz
911080p2x10064:271:1371.25@100 Hz125.0 kHz2560108029701250100 Hz
921080p2x12064:271:1495.0@119.88/120 Hz150.0 kHz2560108033001250120 Hz
932160p2416:91:1297.0@23.98/24 Hz54.0 kHz3840216055002250Low
942160p2516:91:1297.0@25 Hz56.25 kHz3840216052802250Low
952160p3016:91:1297.0@29.97/30 Hz67.5 kHz3840216044002250Low
962160p5016:91:1594.0@50 Hz112.5 kHz384021605280225050 Hz
972160p6016:91:1594.0@60 Hz135.0 kHz384021604400225060 Hz
982160p24256:1351:1297.0@23.98/24 Hz67.5 kHz4096216055002250Low
992160p25256:1351:1297.0@25 Hz112.5 kHz4096216052802250Low
1002160p30256:1351:1297.0@29.97/30 Hz135.0 kHz4096216044002250Low
1012160p50256:1351:1594.0@50 Hz112.5 kHz409621605280225050 Hz
1022160p256:1351:1594.0@60 Hz135.0 kHz409621604400225060 Hz
1032160p2464:274:3297.0@23.98/24 Hz67.5 kHz3840216055002250Low
1042160p2564:274:3297.0@25 Hz112.5 kHz3840216052802250Low
1052160p3064:274:3297.0@29.97/30 Hz135.0 kHz3840216044002250Low
1062160p5064:274:3594.0@50 Hz112.5 kHz384021605280225050 Hz
1072160p64:274:3594.0@60 Hz135.0 kHz384021604400225060 Hz
108720p4816:91:190.0@47.96/48 Hz36.0 kHz12807202500750Low
109720p4864:274:390.0@47.96/48 Hz36.0 kHz12807202500750Low
110720p2x4864:2764:6399.0@47.96/48 Hz36.0 kHz16807202750825Low
1111080p4816:91:1148.5@47.96/48 Hz54.0 kHz1920108027501125Low
1121080p4864:274:3148.5@47.96/48 Hz54.0 kHz1920108027501125Low
1131080p2x4864:271:1198.0@47.96/48 Hz52.8 kHz2560108037501100Low
1142160p4816:91:1594.0@47.96/48 Hz108.0 kHz3840216055002250Low
1152160p48256:1351:1594.0@47.96/48 Hz108.0 kHz4096216055002250Low
1162160p4864:274:3594.0@47.96/48 Hz108.0 kHz3840216055002250Low
1172160p10016:91:11188.0@100 Hz225.0 kHz3840216052802250100 Hz
1182160p12016:91:11188.0@119.88/120 Hz270.0 kHz3840216044002250120 Hz
1192160p10064:274:31188.0@100 Hz225.0 kHz3840216052802250100 Hz
1202160p12064:274:31188.0@119.88/120 Hz270.0 kHz3840216044002250120 Hz
1212160p2x2464:271:1396.0@23.98/24 Hz52.8 kHz5120216075002200Low
1222160p2x2564:271:1396.0@25 Hz55.0 kHz5120216072002200Low
1232160p2x3064:271:1396.0@29.97/30 Hz66.0 kHz5120216060002200Low
1242160p2x4864:271:1742.5@47.96/48 Hz118.8 kHz5120216062502450Low
1252160p2x5064:271:1742.5@50 Hz112.5 kHz512021606600225050 Hz
1262160p2x64:271:1742.5@60 Hz135.0 kHz512021605500225060 Hz
1272160p2x10064:271:11485.0@100 Hz225.0 kHz5120216066002250100 Hz
128—192reserved, value range is used in SVD to indicate native timing for numbers 1—64.
1932160p2x12064:271:11485.0@119.88/120 Hz270.0 kHz5120216055002250120 Hz
1944320p2416:91:11188.0@23.98/24 Hz108.0 kHz76804320110004500Low
1954320p2516:91:11188.0@25 Hz110.0 kHz76804320108004400Low
1964320p3016:91:11188.0@29.97/30 Hz132.0 kHz7680432090004400Low
1974320p4816:91:12376.0@47.96/48 Hz216.0 kHz76804320110004500Low
1984320p5016:91:12376.0@50 Hz220.0 kHz7680432010800440050 Hz
1994320p16:91:12376.0@60 Hz264.0 kHz768043209000440060 Hz
2004320p10016:91:14752.0@100 Hz450.0 kHz76804320105604500100 Hz
2014320p12016:91:14752.0@119.88/120 Hz540.0 kHz7680432088004500120 Hz
2024320p2464:274:31188.0@23.98/24 Hz108.0 kHz76804320110004500Low
2034320p2564:274:31188.0@25 Hz110.0 kHz76804320108004400Low
2044320p3064:274:31188.0@29.97/30 Hz132.0 kHz7680432090004400Low
2054320p4864:274:32376.0@47.96/48 Hz216.0 kHz76804320110004500Low
2064320p5064:274:32376.0@50 Hz220.0 kHz7680432010800440050 Hz
2074320p64:274:32376.0@60 Hz264.0 kHz768043209000440060 Hz
2084320p10064:274:34752.0@100 Hz450.0 kHz76804320105604500100 Hz
2094320p12064:274:34752.0@119.88/120 Hz540.0 kHz7680432088004500120 Hz
2104320p2x2464:271:11485.0@23.98/24 Hz118.8 kHz102404320125004950Low
2114320p2x2564:271:11485.0@25 Hz110.0 kHz102404320135004400Low
2124320p2x3064:271:11485.0@29.97/30 Hz135.0 kHz102404320110004500Low
2134320p2x4864:271:12970.0@47.96/48 Hz237.6 kHz102404320125004950Low
2144320p2x5064:271:12970.0@50 Hz220.0 kHz10240432013500440050 Hz
2154320p2x64:271:12970.0@60 Hz270.0 kHz10240432011000440060 Hz
2164320p2x10064:271:15940.0@100 Hz450.0 kHz102404320132004500100 Hz
2174320p2x12064:271:15940.0@119.88/120 Hz540.0 kHz102404320110004500120 Hz
2182160p100256:1351:11188.0@100 Hz225.0 kHz4096216052802250100 Hz
2192160p120256:1351:11188.0@119.88/120 Hz270.0 kHz4096216044002250120 Hz

Notes: Parentheses indicate instances where pixels are repeated to meet the minimum speed requirements of the interface. For example, in the 720x240p case, the pixels on each line are double-clocked. In the (2880)x480i case, the number of pixels on each line, and thus the number of times that they are repeated, is variable, and is sent to the DTV monitor by the source device.

Increased Hactive expressions include “2x” and “4x” indicate two and four times the reference resolution, respectively.

Video modes with vertical refresh frequency being a multiple of 6 Hz (i.e. 24, 30, 60, 120, and 240 Hz) are considered to be the same timing as equivalent NTSC modes where vertical refresh is adjusted by a factor of 1000/1001. As VESA DMT specifies 0.5% pixel clock tolerance, which 5 times more than the required change, pixel clocks can be adjusted to maintain NTSC compatibility; typically, 240p, 480p, and 480i modes are adjusted, while 576p, 576i and HDTV formats are not.

  • The EIA/CEA-861 and 861-A standards included only numbers 1–7 and numbers 17–22 (only in -A) above (but not as short video descriptors which were introduced in EIA/CEA-861-B) and are considered primary video format timings.
  • The EIA/CEA-861-B standard has the first 34 short video descriptors above. It is used by HDMI 1.0–1.2a.
  • The EIA/CEA-861-C and -D standards have the first 59 short video descriptors above. EIA/CEA-861-D is used by HDMI 1.3–1.3c.
  • The EIA/CEA-861-E standard has the first 64 short video descriptors above. It is used by HDMI 1.4–1.4b.
  • The CTA-861-F standard has the first 92 short video descriptors above. It is used by HDMI 2.0–2.0b.
  • The CTA-861-G standard has the full list of 154 (1–127, 193–219) short video descriptors above. It is used by HDMI 2.1.

A Vendor Specific Data Block (if any) contains as its first three bytes the vendor's IEEE 24-bit registration number, LSB first. For HDMI, it is always 00 0C 03 for HDMI Licensing, LLC. It is followed by a two byte source physical address, LSB first. The source physical address provides the CEC physical address for upstream CEC devices. The remainder of the Vendor Specific Data Block is the "data payload",which can be anything the vendor considers worthy of inclusion in this EDID extension block. HDMI 1.3a specifies some requirements for the data payload. See that spec for detailed info on these bytes:

Vendor Specific Data Block
Byte Description
0 Data block header
1–3 IEEE Registration Identifier (little endian)
4–5 Components of Source Physical Address (see section 8.7 of HDMI 1.3a)
6 (optional) 1, supported; 0, unsuported:
Bit 7A function that needs info from ACP or ISRC packets (Supports_AI)
Bit 616-bit-per-channel deep color (DC_48bit)
Bit 512-bit-per-channel deep color (DC_36bit)
Bit 410-bit-per-channel deep color (DC_30bit)
Bit 34:4:4 in deep color modes (DC_Y444)
Bit 2Reserved, 0
Bit 1Reserved, 0
Bit 0DVI Dual Link Operation (DVI_Dual)
7 (optional) Maximum TMDS frequency. 0, unspecified; else, Max_TMDS_Frequency / 5 MHz
8 (optional) Latency fields indicators 1, present; 0, absent:
Bit 7Latency fields (latency_fields)
Bit 6Interlaced latency fields (i_latency_fields). Absent if latency fields are absent.
Bits 5–0Reserved, 0
9 (optional) Video latency (if indicated, value = 1 + ms/2 with a max. of 251 meaning 500 ms)
10 (optional) Audio latency (video delay for progressive sources, same units as above)
11 (optional) Interlaced video latency (if indicated, same units as above)
12 (optional) Interlaced audio latency (video delay for interlaced sources, same units as above)
13+ Additional bytes may be present, but the HDMI spec. says they shall be 00.

If a Speaker Allocation Data Block is present, it will consist of three bytes. The second and third are reserved (all 0), but the first contains information about which speakers are present in the display device:

Speaker Allocation Data Block
Byte Description
0 Data block header
1 1, present; 0, absent:
Bit 7Reserved, 0
Bit 6Rear left and right center
Bit 5Front left and right center
Bit 4Rear center
Bit 3Rear left and right
Bit 2Front center
Bit 1Low-frequency effects (LFE)
Bit 0Front left and right
2–3 Reserved, 00 00


  1. "High-Definition Multimedia Interface Specification Version 1.3a" (PDF). 10 November 2006. Archived from the original (PDF) on 5 March 2016. Retrieved 2017-04-01.
  2. "read-edid". Polypux.org. Retrieved 2017-04-01.
  3. "Utilities | PowerStrip". EnTech Taiwan. 2012-03-25. Retrieved 2017-04-01.
  4. "SwitchResX - The Most Versatile Tool For Controlling Screen Resolutions On Your Mac". Madrau.com. Retrieved 2017-04-01.
  5. Harald Schweder (2003-02-11). "DisplayConfigX". 3dexpress.de. Retrieved 2017-04-01.
  6. Brezenski (2009-08-07). "Custom Resolutions on Intel Graphics". Software.intel.com. Retrieved 2009-11-04.
  7. VESA E-EDID Standard, Release A, Revision 2. September 25, 2006
  8. VESA Enhanced EDID Standard (PDF), Video Electronics Standards Association, 2000-02-09, p. 32, retrieved 2011-11-19
  9. "A DTV Profile for Uncompressed High Speed Digital Interfaces". 4 June 2013. CEA-861-F. Archived from the original on 2013-08-21. Retrieved 2013-08-15.
  10. Paul Ploumis (2013-07-16). "CEA publishes new high-speed CEA-861-F DTV Interface Standard". Scrapmonster.com. Retrieved 2017-04-01.
  11. "A DTV Profile for Uncompressed High Speed Digital Interfaces" (PDF). 29 November 2017. CTA-861-G. Archived from the original (PDF) on 2017-11-30. Retrieved 2017-11-30.
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