Bus contention, in computer design, is an undesirable state of the bus in which more than one device on the bus attempts to place values on the bus at the same time. Most bus architectures require their devices to follow an arbitration protocol carefully designed to make the likelihood of contention negligible. However, when devices on the bus have logic errors, manufacturing defects, or are driven beyond their design speeds, arbitration may break down and contention may result. Contention may also arise on systems which have a programmable memory mapping when illegal values are written to the registers controlling the mapping.
Most small-scale computer systems are carefully designed to avoid bus contention on the system bus. They use a single device, called bus arbiter, that controls which device is allowed to drive the bus at each instant, so bus contention never happens in normal operation. The standard solution to bus contention between memory devices, such as EEPROM and SRAM, is the three-state bus with a bus arbiter.
Some networks, such as token ring, are also designed to avoid bus contention, so bus contention never happens in normal operation.
Most networks are designed with hardware robust enough to tolerate occasional bus contention on the network. CAN bus, ALOHAnet, Ethernet, etc., all experience occasional bus contention in normal operation, but use some protocol (such as Multiple Access with Collision Avoidance, carrier-sense multiple access with collision detection, or automatic repeat request) to minimize the times that contention occurs, and to re-send data that was corrupted in a packet collision.
Bus contention is the kind of telecommunication contention that occurs when all communicating devices communicate directly with each other through a single shared channel, and contrasted with "network contention" that occurs when communicating devices communicate indirectly with each other, through point-to-point connections through routers or bridges.
- Tanenbaum, Andrew (1990), Structured Computer Organization (3rd ed.), Prentice Hall, pp. 121–124, ISBN 0-13-852872-1.
- Ian Sinclair; John Dunton. "Practical Electronics Handbook" 2013. section "Three-state control". p. 208.
- Theodoros Konstantakopoulos, Jonathan Eastep, James Psota, and Anant Agarwal. "Energy Scalability of On-Chip Interconnection Networks in Multicore Architectures".