The FLAGS register is the status register in Intel x86 microprocessors that contains the current state of the processor. This register is 16 bits wide. Its successors, the EFLAGS and RFLAGS registers, are 32 bits and 64 bits wide, respectively. The wider registers retain compatibility with their smaller predecessors.
The fixed bits at bit positions 1, 3 and 5, and carry, parity, adjust, zero and sign flags are inherited from an even earlier architecture, 8080 and 8085. The adjust flag used to be called auxiliary carry bit in 8080 and half-carry bit in the Zilog Z80 architecture.
|Intel x86 FLAGS register|
|0||0x0001||CF||Carry flag||Status||CY(Carry)||NC(No Carry)|
|1||0x0002||Reserved, always 1 in EFLAGS|
|2||0x0004||PF||Parity flag||Status||PE(Parity Even)||PO(Parity Odd)|
|4||0x0010||AF||Adjust flag||Status||AC(Auxiliary Carry)||NA(No Auxiliary Carry)|
|6||0x0040||ZF||Zero flag||Status||ZR(Zero)||NZ(Not Zero)|
|8||0x0100||TF||Trap flag (single step)||Control|
|9||0x0200||IF||Interrupt enable flag||Control||EI(Enable Interrupt)||DI(Disable Interrupt)|
|11||0x0800||OF||Overflow flag||Status||OV(Overflow)||NV(Not Overflow)|
|12-13||0x3000||IOPL||I/O privilege level (286+ only), |
always 1 on 8086 and 186
|14||0x4000||NT||Nested task flag (286+ only), |
always 1 on 8086 and 186
always 1 on 8086 and 186,
always 0 on later models
|16||0x0001 0000||RF||Resume flag (386+ only)||System|
|17||0x0002 0000||VM||Virtual 8086 mode flag (386+ only)||System|
|18||0x0004 0000||AC||Alignment check (486SX+ only)||System|
|19||0x0008 0000||VIF||Virtual interrupt flag (Pentium+)||System|
|20||0x0010 0000||VIP||Virtual interrupt pending (Pentium+)||System|
|21||0x0020 0000||ID||Able to use CPUID instruction (Pentium+)||System|
All FLAGS registers contain the condition codes, flag bits that let the results of one machine-language instruction affect another instruction. Arithmetic and logical instructions set some or all of the flags, and conditional jump instructions take variable action based on the value of certain flags. For example,
jz (Jump if Zero),
jc (Jump if Carry), and
jo (Jump if Overflow) depend on specific flags. Other conditional jumps test combinations of several flags.
FLAGS registers can be moved from or to the stack. This is part of the job of saving and restoring processor context, against a routine such as an interrupt service routine whose changes to registers should not be seen by the calling code. Here are the relevant instructions:
- The PUSHF and POPF instructions transfer the 16-bit FLAGS register.
- PUSHFD/POPFD (introduced with the i386 architecture) transfer the 32-bit double register EFLAGS.
- PUSHFQ/POPFQ (introduced with the x64 architecture) transfer the 64-bit quadword register RFLAGS.
The ability to push and pop FLAGS registers lets a program manipulate information in the FLAGS in ways for which machine-language instructions do not exist. For example, the
std instructions clear and set the direction flag (DF), respectively; but there is no instruction to complement DF. This can be achieved with the following assembly code:
pushf ; Use the stack to transfer the FLAGS pop ax ; ...into the AX register push ax ; and copy them back onto the stack for storage xor ax, 400h ; Toggle (complement) DF only; other bits are unchanged push ax ; Use the stack again to move the modified value popf ; ...into the FLAGS register ; Insert here the code that required the DF flag to be complemented popf ; Restore the original value of the FLAGS
By manipulating the FLAGS register, a program can determine the model of the installed processor. For example, the alignment flag can only be changed on the 486 and above. If the program tries to modify this flag and senses that the modification did not persist, the processor is earlier than the 486.
- Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). 1. May 2012. pp. 3–21.
- Intel 64 and IA-32 Architectures Software Developer’s Manual (PDF). 1. Dec 2016. p. 78.
- "Silicon reverse engineering: The 8085's undocumented flags". www.righto.com. Retrieved 2018-10-21.
- Intel 64 and IA-32 Architectures Software Developer’s Manual (PDF). 2B. May 2012.